Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits over the past few decades. To enhance transistor performance further, strain may be introduced in the transistor channel for improving carrier mobility. Therefore, strain-induced mobility enhancement is another way to improve transistor performance in addition to device scaling. Several existing approaches of introducing strain in the transistor channel region have been proposed.
There are several existing approaches of introducing strain in the transistor channel region to enhance further transistor performance. In one conventional approach, a relaxed silicon germanium (SiGe) buffer layer 102 is provided beneath the channel region, as shown in FIG. 1(a). The relaxed SiGe buffer layer 102 has a larger lattice constant compared to relaxed Si 104, and a thin layer of epitaxial Si 106 grown on relaxed SiGe 102 will have its lattice stretched in the lateral direction, i.e. it will be under biaxial tensile strain. This is illustrated in FIG. 1(b). Therefore, a transistor formed on the epitaxial strained silicon layer 106 will have a channel region that is under biaxial tensile strain. In this approach, the relaxed SiGe buffer layer 102 can be thought of as a stressor that introduces strain in the channel region. The stressor, in this case, is placed below the transistor channel region. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the abovementioned approach, the epitaxial silicon layer 106 is strained before the formation of the transistor. Therefore, there are concerns about possible strain relaxation upon subsequent CMOS processing where high temperatures are used. An example of a high temperature process step in CMOS processing is the formation of an isolation structure, such as shallow trench isolation, to electrically isolate devices from one another.
In a conventional shallow trench isolation structure, as shown in FIG. 2, a silicon oxide liner 204 is typically thermally grown at temperatures ranging from 900 to 1100 degrees Celsius. The high temperatures can potentially cause strain relaxation and reduce the tensile strain in the tensile strained silicon channel region 206. By using the conventional oxide-filled trench isolation structure 208 with the strained silicon substrate 210, as shown in FIG. 2, the trench isolation structure 208 contributes a significant compressive strain component 212 to the channel region 206. The compressive strain component 212 contributed by the oxide-filled trench isolation structure 208 cancels out a portion of the tensile strain component of the tensile strained silicon substrate 210 constituting the channel region 206. With the reduction of the tensile strain in the channel region 206 of the transistor, the strain-induced performance enhancement is reduced significantly. The compressive strain results from sidewall oxidation and volume expansion of the silicon oxide material in the trench.
What is needed is an improved isolation structure for strained channel transistors and the method for making same.